A SystemVerilog implementation of the Eyeriss CNN architecture includes Network-on-Chip (NoC) optimization to maximize data reuse. Additionally, it incorporates approximate multipliers to improve both speed and energy efficiency. Implemented using ASAP7 Predictive PDK.
"}},{"node":{"frontmatter":{"title":"Metis: A Neuromorphic IC","cover":{"childImageSharp":{"gatsbyImageData":{"layout":"constrained","placeholder":{"fallback":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABQAAAAPCAYAAADkmO9VAAAACXBIWXMAAA7EAAAOxAGVKw4bAAADIklEQVQ4y3WT3U+bZRyG92fYnaBOGjYm9PttS/u8b7sWJuPDaGSOWKBfVCJzxo94wIwJY9PINo1T5MTNgTEmOuOJSsG2pCbGf2CJZxpA2rcfGWA/3haSy7T1wCAc3AfPyZX7l+e+TkTdRr6+aOfesxJLQ3bujjj44jkHS8N2lgftLDUy1MrygJ37A3a+GXJyWZhoa9dzpqODjv/kxEcXbPCmzN6UjBYT7LzloXTFQ3VKUA8paFG5lUmZekSmEpEh5uXeBTuPnWqn8/Qh4Ad+G39PCzZDbv4KCv54RWEjppANusmNC7JBgTohyAYE6iWZ7Usy1ZDCp89I6E7p6Tzc8KbfRnVaZnvSTfFdB9vvuch/aKcQFBQCMvmgYCuqoM64eHTDQWHWgRZRWDwvoXvqKGCfjcrLCsXbVuq/PM1+8iy1RDel70zsXZPIjytsfC5TSZrQUkYq6W52F8/xSb+Tk0edfLPXxt6UwsacC/WBxO9f+tn50crBb53kH1hJv/0Cu3En+4kuqnEz1dVuWHdyZ1Tm5ONHAq3s3ZHJfOug9IMF9XsXxRWJwrLEw/d9JGefp7pmRls1oq0ZKccNkLKxEOpB13YE8NaLZkgb0ZJd1H42cJDoQksbUa8Ktke8qK/LlJNm9hMGtLiJypoBfjWxOGlB16an88zhhg1gwkwpbkBbNaHFjVTWzRTfcVMMuFEjHrZuedn9yYy2buTRiomD+xILwxK6J/X/bzg/YoG0GS3V1TyrFjdSTZkozAjyAZlc1I06ppB9VbAz4yRz2UV1wnP8L8+ft1Ka97D5lUBLGKilDJRXzBSvCPLjglxUUAgLCuOCwqhM7iXBfljhs/7jduizUZvwsBmSyV31k7/tpfiaqwUICnIRQT7USnGiNfJ6A3jcsBum1CIymUAPW6FB/owNkh91ozbajQkyYTfZUAvUMCczJpqmLBwH/LhPgikv5bCgND3MzhtD1MMCLeKhFlaoxpTm8LWo0nyXw0rT5bsDx7h8UTLQsGXOZ+ZaXw+z/U5unLNw3WdtZq7Xwlyvlev+f98+Cw0ZAg4DT7TrOX2o4T+bGKV9zn8UJwAAAABJRU5ErkJggg=="},"images":{"fallback":{"src":"/static/b304832fc8abf9a826a15b4c1a21d2a0/6dd20/layout.png","srcSet":"/static/b304832fc8abf9a826a15b4c1a21d2a0/d8ee9/layout.png 175w,\n/static/b304832fc8abf9a826a15b4c1a21d2a0/9a054/layout.png 350w,\n/static/b304832fc8abf9a826a15b4c1a21d2a0/6dd20/layout.png 700w","sizes":"(min-width: 700px) 700px, 100vw"},"sources":[{"srcSet":"/static/b304832fc8abf9a826a15b4c1a21d2a0/ea096/layout.avif 175w,\n/static/b304832fc8abf9a826a15b4c1a21d2a0/d9301/layout.avif 350w,\n/static/b304832fc8abf9a826a15b4c1a21d2a0/16978/layout.avif 700w","type":"image/avif","sizes":"(min-width: 700px) 700px, 100vw"},{"srcSet":"/static/b304832fc8abf9a826a15b4c1a21d2a0/93fe5/layout.webp 175w,\n/static/b304832fc8abf9a826a15b4c1a21d2a0/320a2/layout.webp 350w,\n/static/b304832fc8abf9a826a15b4c1a21d2a0/fbd00/layout.webp 700w","type":"image/webp","sizes":"(min-width: 700px) 700px, 100vw"}]},"width":700,"height":524}}},"tech":["Verilog","MAGIC","OpenLane","Xschem","Python"],"github":"https://github.com/Karthikeyan564/Metis","external":"https://drive.google.com/file/d/1cPj87hYUuPW9w9CtdHkBwdebi8O6tIhc/view?usp=sharing","cta":null},"html":"A programmable 256-neuron, 265*8-synapse neuromorphic chip in 130nm CMOS is developed to accelerate inference and learning for a large number of classes of spiking neural networks(SNNs). The chip features an analog circuit for leaky integrate-and-fire neuron models, on-chip e-prop learning.
"}},{"node":{"frontmatter":{"title":"GPS Baseband IC","cover":{"childImageSharp":{"gatsbyImageData":{"layout":"constrained","placeholder":{"fallback":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABQAAAAPCAYAAADkmO9VAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAC6ElEQVQ4y32TXWtcVRSG+1usZuKFnrPX3mcSU0nttYGktCAIitXUC0UploofWJAiWm9asJhM2/k808lMJjMZp9FeSVuwxAj2xn+gVzU5HzPnTDKZVB6ZM16IzXixYW3Y61nv+y72kcnJSf59JiZSXJy1yC0YluYMmZNCZl6TmdNJfeNVxfXh/WVDZs5heV5YWhAKpw0fnnieI08An5lg89QUg/Mv4b9/nGhpit1vp4m/nmEv77Cb18RfztC9PENv+QWii8fwz83y10cnuPOKcxgwxY8Labzzs/zxyTEeZTWeq/lz2WE7p9nJa3ayhu28YacsbF81/P7ui4QXjtM8bQ4H3j3l0MtM4a8Ifk7wcobOsC6l8bJpunVFtyp4WQf/hubRlTT94hTtN2U8cC+fpttS+FlNeEvotS2iusbPG7oVm25VEZQNUd0mqAiDumHjPXsMcD5N79p08tDPCGFJJ43Rqs3OsibIKaJVReAaujWFlxX2yw4b76j/AJ+dZOJointvCPt1TVhTdGt20hSv2URrCr9gkgFxyyYoGjquwssJ/WKa9hk5BPhUintvKwZNwa9qooZNvDo8Fp2KJijoxG7cGA7SdCoqGXxQd7i9OAZ4f1F4/J2i01T0Wja9tk3ctOm4mrBsCFeEuKmI14cL0/glxUFD88MFa4zCReHgtqLTUgloaC9uWsQtRXhL4+UliaDXVkRrQrAiHNSFjXPWmAwXhf7q0PIow7gxAkcNRVAS/LwaLakmhCuGsGYzqGra45Zy/4ywP8wnUWclSjqVf5pdTXBTkgzDsiZwR5b3bv7PUu6eFQbrQneY3fcWQc3GL45+SOAqwpIQVoWgKviu4LmK3aJD++wYhQ/e0tAS9u9Y9FuK3TVhrynEFU1U0ESupr8u9Nc1UVETFgz9azNsvK6fBD59NEXpNZvfvlE8vP4cv1612PxK8ctl4ecvhAefClsfG7YuCZufabYuKX76XPHwg2mWTir+BrXHwntXnMvHAAAAAElFTkSuQmCC"},"images":{"fallback":{"src":"/static/3da957d4ed67ff8ed89a4585ea8e8eeb/6dd20/layout.png","srcSet":"/static/3da957d4ed67ff8ed89a4585ea8e8eeb/d8ee9/layout.png 175w,\n/static/3da957d4ed67ff8ed89a4585ea8e8eeb/9a054/layout.png 350w,\n/static/3da957d4ed67ff8ed89a4585ea8e8eeb/6dd20/layout.png 700w","sizes":"(min-width: 700px) 700px, 100vw"},"sources":[{"srcSet":"/static/3da957d4ed67ff8ed89a4585ea8e8eeb/ea096/layout.avif 175w,\n/static/3da957d4ed67ff8ed89a4585ea8e8eeb/d9301/layout.avif 350w,\n/static/3da957d4ed67ff8ed89a4585ea8e8eeb/16978/layout.avif 700w","type":"image/avif","sizes":"(min-width: 700px) 700px, 100vw"},{"srcSet":"/static/3da957d4ed67ff8ed89a4585ea8e8eeb/93fe5/layout.webp 175w,\n/static/3da957d4ed67ff8ed89a4585ea8e8eeb/320a2/layout.webp 350w,\n/static/3da957d4ed67ff8ed89a4585ea8e8eeb/fbd00/layout.webp 700w","type":"image/webp","sizes":"(min-width: 700px) 700px, 100vw"}]},"width":700,"height":524}}},"tech":["Verilog","OpenLane","Python","Verilator"],"github":"https://github.com/ISL-ECE-CEG-AU/GPS_Baseband","external":null,"cta":null},"html":"The entire GPS baseband functionality is realized using a combination of custom designed logic functionality GPS Engine (ASIC portion) and the on chip RISCV microprocessor to provide the complete position fix starting from the digitized IF input bits.
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