{"data":{"jobs":{"edges":[{"node":{"frontmatter":{"title":"Co-Founder and Digital Design Engineer","company":"HelixLogic","location":"Chennai, India","range":"December 2022 - Present","url":"http://www.uicbannauniv.com"},"html":"<!-- - Designed and Implemented an ASIC in SystemVerilog to decode DNA sequences based on signals derived from a Nanopore Membrane.\n- Startup funded by the Indian Government’s BIRAC EYUVA program.\n- Managing a two-member student team. -->\n<ul>\n<li>Co-founded an ASIC design startup focused on Ultrafast, Nanopore DNA sequencing, raising $10,000 in startup capital in the first year.</li>\n<li>Designed and Implemented an RISC-V V-extension based ASIC in SystemVerilog to decode DNA sequences based on signals derived from a Nanopore Membrane.</li>\n<li>Achieved a cycle-to-cycle acceleration factor of 107 at 400 MHz on benchmarks as compared to a Tesla V100.</li>\n<li>Managed a 2-member undergraduate student team.</li>\n<li>Patent Pending for the basecaller IC architecture.</li>\n</ul>"}},{"node":{"frontmatter":{"title":"Undergraduate Researcher","company":"University of Toronto","location":"Toronto, Canada","range":"May - August 2022","url":"https://www.eecg.utoronto.ca/~roman/lab/index.html"},"html":"<!-- - Summer Internship under Prof. Roman Genov at the University of Toronto funded by MITACS.\n- Developed a RISC-V core(in SystemVerilog) to create custom mask sequences on the fly for the coded-exposure image sensors.\n- Worked on mask generation and mask decompression modules for generating hard-coded masks and receiving compressed masks. -->\n<ul>\n<li>Developed a RISC-V core in SystemVerilog to create custom mask sequences on the fly for the coded-exposure image sensors.</li>\n<li>Performed verification of the RISC-V core through OpenOCD on a Nexys Video Artix-7 FPGA.</li>\n<li>Improved the Mask generation and Mask decompression modules for generating hard-coded masks and receiving compressed masks leading to a 24.47% gain in performance.</li>\n</ul>"}},{"node":{"frontmatter":{"title":"Summer Reseach Intern","company":"Indian Academy of Sciences","location":"Bengaluru, India","range":"June - July 2021","url":"https://www.ias.ac.in/"},"html":"<!-- - Developed Image-based-rendering based Reinforcement learning environment for end-to-end training to avoid sim2real, domain adaptation or domain randomization etc using CUDA and OpenGL -->\n<ul>\n<li>Developed a Image-Based-Rendering (IBR) based Reinforcement learning environment for end-to-end training to avoid sim2real, domain adaptation or domain randomization etc using CUDA and OpenGL.</li>\n<li>Achieved a 67% better model transfer rate than Sim2real while achieving a 2.57x FPS speedup.</li>\n</ul>"}},{"node":{"frontmatter":{"title":"Undergraduate Researcher","company":"CEG, Anna University","location":"Chennai, India","range":"May 2021 - January 2022","url":"https://www.annauniv.edu/"},"html":"<!-- - Implemented RTL changes(in Verilog) to accommodate the modified architecture of the ASIC.\n- Wrote test benches to simulate and verify the behavioral functioning of any given module -->\n<ul>\n<li>Designed a GPS Baseband Engine as a team of 4 students using OpenLane and sky130 PDK.</li>\n<li>Selected by SSCS PICO Contest for fabrication.</li>\n<li>Implemented RTL changes to accommodate modified architecture of the ASIC.</li>\n</ul>"}}]}}}